In order to increase the yield in fabricating memories with high storage capacity, which use extremely fine integration technologies which are therefore difficult to implement without defect, it is usual to provide entire lines (in rows or in columns) of redundancy elements.
If the testing of the memory reveals that a row or a column of memory cells is defective, it is replaced by a row or a column of redundancy elements. Seen from outside the integrated circuit, the memory should then appear to be completely serviceable: the implementation of the redundancy is transparent for the user.
In what follows, the word "line" will be used whenever it is desired to speak non-specifically of a row or of a column, and the columns and the rows of the array will be distinguished in the usual way: the memory cells of the matrix array are connected in rows and in columns; all the cells of a single column are connected to the same column conductor (called bit line) on which information may be read or written, and all the cells of a single row are connected to the same row conductor (called word line) which serves to address a particular row of cells. In the case of the most complex memories, there may be a row decoder which designates a particular row, and a column decoder which designates a particular group of columns in order to route the bit lines corresponding to this group to the data input/output leads of the integrated circuit.
Several redundancy circuit architectures have already been proposed. One possible architecture is that in which at least one redundancy line (row or column) is placed beside a group of lines (rows or columns), in such a way as to be able to replace any defective line of this group by the redundancy line. A fuse is associated with each line capable of being replaced; the fuse is blown in order to isolate the defective line from the rest of the circuit and in order to connect the redundancy line in its place.
Other architectures make provision for not just one fuse associated with each line capable of being defective, but a battery of n fuses associated with a group of lines in which a replacement may be able to be effected; the battery makes it possible to store the address of the defective line (a k-bit address requires a battery of k fuses). This battery, that is to say a group of k fuses, is coupled to a comparator which receives an address applied to the input of the memory; if the address applied to the memory is exactly equal to the defective address stored in memory by the battery, the comparator causes disconnection of the defective line and connection of the replacement line.
The implementation of redundancy poses a problem which is that of the efficiency of blowing of the fuses. This efficiency is not 100% and it happens that a fuse which it is desired to blow proves in reality to be poorly blown, without the possibility of repeating the blowing operation. By blowing of the fuse is meant either the open-circuiting of a fuse which was conducting in the intact state, or, on the contrary, the putting into the conducting state of a fuse which was not conducting in the intact state.
Among the general objectives when producing an integrated-circuit memory must be the improvement of the overall repair efficiency when employing redundancy.
There is also the ease of a complete test of the memory, including the redundancy elements, and including the unused redundancy elements. It has been seen, in fact, that in certain cases it was not sufficient for the memory to be serviceable overall with the redundancy elements which were put into service in order to repair defects: it is necessary furthermore for the unused redundancy elements not to exhibit defects which would entail the memory not being in conformity with certain specifications, for example an exaggerated current consumption as a result of leaks in the region of the unused redundancy elements. However, the unused redundancy elements are very difficult of access and it is not always possible to test them.
Another objective for a memory may sometimes be the possibility for repair, not only at the time of fabrication (in the course of the test on the wafer), but also during use.
Finally, one objective must always be transparency with regard to the user, who must not see the difference between a memory which has required repair of a defect to be undertaken and a memory which has not required this repair. However, more often, the additional connections added to gain access to the repair line lengthen the information access time for the repaired addresses with respect to the information access time for the normal addresses.